The present invention relates to a method of manufacturing a semiconductor device. More particularly, it relates to techniques effectively utilized for, for example, a semiconductor device which has both regions doped with P-type and N-type impurities and which includes a gate and/or wiring of a laminate structure of silicide/polysilicon.
With the requirement of manufacture of micro semiconductor devices, fine element forming processes the minimum processing dimension of which is 1.3 .mu.m or less have been developed.
In a semiconductor device, for example, a gate array produced by the fine element forming process, the resistance of each gate electrode, which has been conventionally formed of a polysilicon layer, affects the delay of a signal. Accordingly, a "polycide" layer which is of a laminate structure consisting of a polysilicon layer and a silicide layer has been applied to the gate electrode. The gate array in which the polycide layer is applied to the gate electrode, is described in U.S. Ser. No. 450,897 filed on Dec. 14, 1989, assigned to the same assignee of this application, U.S. Pat. No. 5,075,753.